1. Field of the Invention
The invention relates to a wafer-level package comprising a printing technique for a small sized IC (integrated circuit) such as a RFID (radio frequency identification) IC, an LED (light emitting diode) IC, a diode IC and the like, which has just a few pins. The wafer-level package is further fabricated into a SMT (surface mounting technology) component after grinding and cutting, and can be then assembled on an antenna or a substrate with SMT.
2. Description of the Related Art
In a conventional chip scale package (CSP), production capability and yield of small sized ICs (integrated circuits) are not high. Each wafer is used to manufacture many chips. The chips are then used to fabricate small sized ICs (integrated circuits) such as an RFID (radio frequency identification) IC, an LED (light emitting diode) IC, a diode IC and the like with a few pins. Since the chips are packaged individually, packaging the chips on a wafer with, for example, 30K chips requires a lot of time. On the other hand, a wafer-level package fabricates the ICs on a wafer as a compete IC rather than individual chips, and cuts the wafers into complete packaged ICs. The production efficiency of the wafer-level package for small IC chips is very high. Because a production unit is based on wafers, the general wafer-level package uses equipment similar to equipment used in semiconductor manufacturing, for example, the semiconductor manufacturing processes of metal sputtering, photo etching, polymer coating, solder ball application and the like. Since the wafer-level package is accomplished on wafers, the manufacturing cost for the wafer-level ICs is very high because the investment cost for the manufacturing equipment is very expensive.
For typical small-sized ICs such as RFID or LED ICs, packaging and assembly efficiency is a crucial factor in the determination of product cost. With reference to FIGS. 1A-1E and 2A-2F, conventional single chip packaging and assembly methods comprise scoring and cutting individual ICs from a wafer, bonding the ICs to a substrate, attaching bonding wires and covering or encapsulating the assembly to form an IC module. The IC module is then connected to an antenna or mounted on a substrate to make a product. Mass production equipment for single chip packaging and assembly is very expensive, and the production capability is rather low, so that product unit price is very high. Furthermore, the single chip package is too thick to make very thin small products.
A number of sequential processes are involved in fabricating and packaging single chip products. First, process of FIG. 1A prepares a wafer (70) with multiple wire pads (72). Process of FIG. 1B is wafer cutting and grinding to form chip (71), wherein each chip (71) has several wire pads (72). Process of FIG. 1C is die bonding and wire bonding, wherein the chip (71) is mounted on a substrate (73) and is connected to wire pads (731) on the substrate (73) via wires (74). Process of FIG. 1D is encapsulating, wherein the chip (71) is encapsulated by packaging material (75). The last process of FIG. 1E is packaging, wherein films (77) are applied to package the encapsulated chip (71).
A flip chip packaging method is used to fabricate thin small products, such as IC cards and RFIDs. A metal bump is formed on the wafer. Then the flip chip method is used to attach the IC to a module or directly connect the IC to an antenna or mount the IC on a substrate after wafer grinding and cutting to form a semi-finished wafer-level package.
A number of sequential processes are involved in fabricating thin small products. First, process of FIG. 2A prepares a wafer (80) with multiple wire pads (81). Process of FIG. 2B is bump forming, wherein multiple metal bumps (82) such as gold bumps are formed on the wire pads (81). Process of FIG. 2C is wafer grinding and cutting to form multiple chips (83). Process of FIG. 2D prepares a substrate (90) on which conductive circuits (92) and a layer of conductive paste (91) such as silver paste are applied. The last two processes of FIGS. 2E and 2F are flip chip assembly, wherein the chip (83) is mounted on the substrate (90) and further encapsulated and packaged by films (100)(101).
However, this fabrication method only can be used for flip chip assembly products and cannot be used for SMD products. Problems with flip chip processes are also low production efficiency and high equipment cost that cause a high product unit price, so this method is not used by many manufacturers.